Precise clock generation is required in a majority of mixed signal ICs. Generally a PLL of some sort is used. In a prior post the concept of clock distribution was explored. The actual clock was generated by an interesting PLL based on a DCO. There are some advantages to this technique when it comes to providing a clock to an AMS system. Interested readers may go to www.signalpro.biz and then navigate to “Engineering_Pages>Engineer’s corner” and look for the ADPLL design… paper.

In relatively high speed analog and mixed signal IC designs, a challenge is to distribute the clock ( usually derived from a clock reference like a PLL) such that clock skew is either eliminated or minimized.In one of our designs, clock distribution was becoming a problem so we studied it and came up with a solution which is illustrated in this posting and its accompanying article under “Engineering Pages” in the website. For a detailed look at this technique, interested readers may go to www.signalpro.biz and then navigate to “engineering_pages>engineer’s corner>clock distribution strategy”.

Collecting the right references for the design of diodes became a fairly serious project. However, this was done and a reasonable collection was generated for both simple p-n junctions and pin diodes. Use of these references can make the job a little easier. The reference list is on the website under “engineer’s corner” in engineering pages.

Need a pn junction diode that has a high reverse breakdown, very low capacitance ( so its fast) and low resistance in the forward direction? If this is the case then a simple pn junction diode may not provide the answer. The reason is, that as the breakdown voltage goes up, the forward resistance goes up, capacitance goes down. If you a need a lot of current then this diode will not provide it. As the resistance goes down the breakdown goes down and the capacitance goes up. So sometimes a simple pn junction diode cannot meet specifications.

Yet if this type of performance is required, either for purposes of high current
(read low resistance ) or high frequency applications then a different type of diode is needed.

This is the P-I-N or N-I-P diode. The I stands for “intrinsic”. This diode has a heavily doped p region and n region, just like in a ordinary pn diode. However, the resemblance ends there. In a P-I-N diode there is a high resistivity ( or
“intrinsic” region) sandwiched between the n and p heavily doped regions. The inclusion of the intrinsic or high resistivity region imparts some very useful characteritics to this structure. These characteristics are explored heuristically in this post.

Resistance: The resistance of the P-I-N diode is inversely proportional to the forward current through the diode and can be controlled by it. Very flat resistance characteristics can be generated this way. The reason for the low resistance with current is that as the high resistive region has very few carriers for recombination, any injected minority carriers coming from the heavily doped p and n regions do not die quickly but persist for “long” lifetimes in the I region. Thus the higher the current, the more free carriers in the I region and the lower the resistance. In the ultimate limit the forward resistance reaches the contact resistance which can be made very low.

Capacitance: The pn junction zero bias capacitance in the P-I-N diode is very low ( or relatively low compared to the ordinary pn junction diode). The reason is that the depletion region ( the region that is completely depleted of carriers with increasing reverse bias or zero bias) forms the “insulator” of a parallel plate capacitance. The parallel plates are, of course, the heavily doped p and n regions of the diode. The higher the resistivity of the I region the wider the depletion region and the lower the capacitance. Also the capacitance is very flat over a wide band of high frequencies so matching with other circuits becomes easier. As a result of the low capacitance the P-I-N diode can switch very fast and can be used in high frequency applications.

Reverse breakdown voltage: The breakdown voltage is high since the breakdown electric field drops voltage across a wider depletion region. As the depletion region becomes wider and wider with reverse voltage the breakdown increases.

Thus if one wants to reconcile high breakdown with low resistance and low capacitance then a P-I-N diode is a great choice. Both power diodes and RF diodes can be made with this technology.

Some disadvantages in the usage of the P-I-N diode are that (a) Its performance can only be predicted accurately if the lifetime of the minority carriers in the I region are known accurately. There are not a lot of analytical techniques to calculate this, therefore for precise usage, measurements need to be made. ( See the previous posts). (b) Most circuit simulator programs such as PSPICE do not provide a mathematical model ( empirical or physics based) so circut simulation is difficult. (c) The fabrication of the diode is slightly more complex. However most vendors provide the parameters and application notes for their P-I-N diodes so usage is made fairly easy. However, designing one from scratch can be quite involved because of the above factors.

As semiconductor designers we grew up with the concept of lifetimes of minority carriers in silicon. Our task was to take the process parameters and design rules from the foundry and fashion a chip. However, once we venture beyond this safe boundry and pit our skills against device design from scratch, a number of issues come up with which we are not too familiar with. One such came up for me this weekend. I was trying to calculate minority carrier lifetimes for specific conditions. I found out that this is a very difficult thing to do. Minority carrier lifetimes vary quite broadly and are dependent on a number of factors. Among these are Auger recombination, band to band recombination and Shockley-Read-Hall (SRH)recombination.

The lifetime is a strong function of the doping concentration of the silicon. It is easier to use analytical formulas for lifetime calculation when the concentration is high ( > 1E17).

High resistivity material is harder to handle analytically. The lifetimes in these materials can be a function of the construction of the crystal(CZ versus FZ). In addition various processing steps can have an impact on the lifetime.

Nevertheless analytical formulas do exist for estimation of lifetimes. The one that I am now using is: lifetime = 5E-7/(1.0 + 2.0E-17)N, where N is the doping concentration in cm**3.

Roulston has published a curve that also shows the approximate variation of lifetime with concentration. Both of these techniques are just approximations. I compared calculations of the lifetime for various concentrations using the analytical formula with Roulston’s curve. The fit became very close as the concentrations increased, but was poor at low concentrations (highly resistive silicon).

My conclusions are that if the need is simply to estimate the lifetime to a rough order of magnitude then by all means one can use the analytical formula given above or Roulston’s curve. However, if precise numbers are required then measurements must be made on samples of doped silicon under the conditions of operation. There is no shortcut here for that kind of accuracy!

Microstrip is the preferred style for designing passive circuitry for MMICs, RF and high speed digital circuits. If the substrate is a board or GaAs the task is simpler and the design can be pretty much cookbook. However, if the designer has to do this on a silicon substrate ( just an ordinary one, say for a SiGe process or fine line CMOS) then it becomes complicated. Why?

The reason is that standard silicon substrates are very lossy for high frequency signals and the design of microstrip ( specially the initial hand calculation/engineering judgement type designs) become a chore. If one is fortunate to have expensive CAD tools that one can use extensively then it is less of a grind. However, one still has to understand how microstrip behaves on silicon and what one has to do to make the right corrections.

A while ago I wrote an article on this precise subject. It is available on the SPG website under the engineering pages> engineer’s corner for interested colleagues. Feedback on this will be greatly appreciated since some of the issues were expounded based on personal observation and experience.

Recently, we at SPG got involved in high speed data transmission issues and in particular the CRC algorithm. The algorithm itself has been around forever it seems, yet its simplicity is very appealing. Anyone involved in it, or about to get involved in data transmission is probably very familiar with it. In any case I found it very interesting.

The basic scoop on it is as follows: ( Interested readers may view the details on our webpage: www.signalpro.biz>engineering_pages>engineer’s corner and look for the detailed article and hardware implementations.)

The CRC procedure can be explained as follows: You have a data message you want to transmit which is k bits long. You can use the CRC to generate another sequence of bits that is n bits long. The latter sequence is called the frame check sequence. What you have to do is actually trasmit both the original k bits of your message and the FCS that is n bits long. Therefore the total length of your transmitted message becomes k + n bits. This k+n bits should be exactly divisible by some predetermined number.

At the receiver the received k+n bit long message is divided by the same predetermined number. If there is no remainder then the message has been received without errors. If there is a remainder then the message has errors. Its as simple as that!

An ever present issue in the design of analog circuits is the challenge of estimating power dissipation, size on silicon, cost etc. We would all like to know these factors as early on as possible. Both designers and customers can benefit from this information. These parameters are very dependent on the specifications and therefore the technology chosen for implementation. As we got to pondering this, a customer did, very bluntly, ask for these estimates for a current source “high speed” DAC. As a result we had to go and look at these design factors. Ultimately it turned out that the results of that little study turned into a report. We published the report and it proved to be very useful indeed, not only for that particular item but for a broad class of analog devices. The report is available at www.signalpro.biz/pcsdac.htm for interested viewers.

This month we got involved in the detailed design of a diode. For most analog and RF ASIC designers diodes are pretty trivial as far as design is concerned. The reason is that we get the parameters from the foundry and use the scaling for diodes already fully characterized by the foundry. However, when we get a specification like: ” Need a diode with a series resistance of 1 ohm, a capacitance of 0.2pF, with a clamping voltage of 25 volts with a 5 Amp current”, things get a little more sticky.

Where do we start? I suppose one set of answers are: (1) Start with the substrate.
(2) Use Irwin’s curves to calculate sheet resistance, (3) Use a manual like the Semiconductor QRM design manual to get an initial design for the required capacitance. This involves extracting (a)The concentration gradient (b) The built in voltage (c) zero bias capacitance… Once all of these preliminary parameters are calculated, we use a simulator like Athena or Atlas ( or other simulation tools like the Stanford University TCAD set) or SYNOPSYS. This is the tricky part where optimization becomes so important and it takes a long time!