The inductance and resistance of the bondwire can play a significant role in the performance of a high performance integrated circuit. This being the case it behooves the design engineer to include these parasitic bond wire components in the final simulations of the chip. Although the most accurate values of these parameters can only be available from the assembly companies for the IC, analytical models have been developed by standards bodies like the JEDEC. A calculator based on these models has been developed and is available here. A very brief paper is also available on these models and has been described elsewhere in these posts. For more information on this please visit the Signal Processing Group Inc. website located at http://www.signalpro.biz.