A VCO is fairly difficult to simulate. When designing a PLL ( phase locked loop) it helps to use a behavioral model of a VCO to begin the design. This is because a behavioral model runs fast and is cheaper in simulation time and engineering time. There are a number of ways to do this. However, a popular way is to use PSPICE ABM modeling to implement the VCO behavioral model. In a recent post Signal Processing Group Inc.’s technical team has released a white paper that describes this. The paper also includes simulation results and the run file used. Interested parties may access this paper from the complementary items link on the SPG website.

In an earlier post ( http://www.signalpro.biz/wordpress/phase-locked-loop-pll-acquisition-behavior-mathematical-expressions/) an approximate expression for the acquisition time of a PLL was tabulated with conditions for its use. The text describing the conditions was left out. The following are the conditions for the use of that expression.

A PLL has multiple phases of operation. One of the early phases is the acquisition of a signal and lock-in to its VCO frequency. This behavior is complex and hard to specify exactly using analytical expressions. However, a number of approximate expressions have been derived that can form the starting point of numerical, iterative analysis. Failing this, it becomes very difficult to even start the design of a PLL. In a recent paper released by Signal Processing Group Inc., these fundamental expressions are examined and presented for interested readers. Please visit the SPG website and use the “complementary” link to access this paper.

After scouring the web for a set of “typical” PLL specifications and not having had much luck we decided to collect and tabulate a set of typical specifications ( by no means complete, but including most of the relevant specifications). These specifications are available in the Signal Processing Group Inc.’s website under the complementary items link. Interested readers are invited to visit the website and the link.

A PLL is a difficult circuit to simulate using active and passive device models on a circuit simulator. Specially if it is a fast PLL. The signals are fast but the time constants of the filter are slow. The circuit simulator can have problems following both fast and slow signals. In addition it usually takes quite a few cycles of frequency to get a reasonable solution. (However if one is prepared to wait then the results can be very accurate at times.) A reasonable solution to  problems of simulation time and circuit simulator issues, is to use behavioral models which tend to very fast in simulation,  but not as accurate. A methodology that employs a mixture of MATLAB analysis, behavioral models and finally detailed circuit simulation is a practical one. Use MATLAB and behavioral models to get close to a solution and then fine tune using circuit simulation. Please vist the Signal Processing Group Inc.’s website for more technical information and ways to engage with us or simply ask questions or insert comments.

A low noise amplifier, a LNA, is an important circuit in many types of RF and wireless systems. It is usually the first circuit to be encountered in an amplifier chain that starts at the output of the antenna. The FRIS formula shows that in a chain of amplifiers, the gain and noise of the first amplifier sets the noise of the entire chain. These amplifiers have a number of specifications that are used in the industry. A white paper published by Signal Processing Group Inc., describes these specifications and  provides their descriptions. Familiarity with these specifications can only result in better designs. Please access this paper from the SPG website. Use the “Complementary” link .

QPSK is a popular format for digital communications. QPSK modulation has been described in this blog in earlier posts. This post describes the coherent demodulation technique for QPSK composite signals. The white paper may be found under the ” Complementary” menu item in the Signal Processing Group Inc. website. 

We keep reading about the complexity and cost of analog and RF/wireless ASICs. It seems to us that this is not an entirely true picture. Analog and RF /wireless ASICs do not necessarily have to be complex or expensive ( in fact is many cases they are deliberately kept simple ( e.g a LNA ). A matched pair of transistors for high frequency or high accuracy service can be an analog or RF/wireless ASIC. A high frequency LC filter or a high frequency monolithic microwave filter can be a RF/wireless ASIC. A simple 32 bit analog EEROM for trimming references and other circuits can be an ASIC. Customized low noise transistors with a small amount of circuitry can be an analog or rf/wireless ASIC. Fabrication can also be relatively low cost. Please visit the Signal Processing Group Inc., website or contact us to discuss your needs. We are sure we can come up with a relatively low cost solution to your analog and Rf/wireless ASIC or module needs.

The mapping between the symbol constellation points for various values of I and Q is described by a set of waveforms. In QPSK there are 4 symbols, labeled 11, 01, 10, 00. So each symbol conveys two bits. These symbols may be coded in a number of ways. A set of graphical displays show one way of doing this. The symbols themselves are also composed of waveforms with differing phases. These waveforms are used to build the composite QPSK signal. This document should be read in conjunction with an earlier brief paper on QPSK. (http://www.signalpro.biz/wordpress/?p=707)

This paper is an attempt to explain how the last line of the graphical QPSK signal waveform was constructed. In that construct two cycles of each symbol waveform were used. Note that negative values are simply drawn by inverting the symbol waveform.

Please visit the Signal Processing Group Inc., website and choose the complimentary items link. The files can be accessed from there.

In a significant number of cases in RF and MW design, signals need to be combined or split ( depending on the application). There are a number of techniques to do this. One of the popular ones is the use of the Wilkinson divider. Invented in 1960, when Wilkinson described a device that separated one signal into n equal signals of equal phase and amplitude. The Wilkinson divider has become a popular way to split or combine signals.The device is bilateral and can be used as a splitter or a combiner.

A brief paper that describes the basics of a 2 way Wilkinson divider/combiner, its basic design equations for a starting design ( that may need to be fine tuned further, depending on the application) and its layout are described in a brief paper released by Signal Processing Group Inc. Please visit our website and check under the “Complimentary Items” link.