In relatively high speed analog and mixed signal IC designs, a challenge is to distribute the clock ( usually derived from a clock reference like a PLL) such that clock skew is either eliminated or minimized.In one of our designs, clock distribution was becoming a problem so we studied it and came up with a solution which is illustrated in this posting and its accompanying article under “Engineering Pages” in the website. For a detailed look at this technique, interested readers may go to www.signalpro.biz and then navigate to “engineering_pages>engineer’s corner>clock distribution strategy”.